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The industry's first digital fully integrated regulator to support SVID and PVID

一月 29 2018 2018-01 Connectors Infineon Technologies
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Infineon Technologies AG introduces the latest integrated point-of-load Power Supply (IPOL) family that combines ease of use with high power density. It is the industry's first fully integrated regulator with PMBUS, SVID, and PVID capabilities and is used to power Intel cpus, low-current POL, chipsets, and ASics/FPgas. It can use up to 50% less space than traditional discrete power solutions and is the smallest solution in its class.

     Infineon Technologies AG introduces the latest integrated point-of-load Power Supply (IPOL) family that combines ease of use with high power density. It is the industry's first fully integrated regulator with PMBUS, SVID, and PVID capabilities and is used to power Intel cpus, low-current POL, chipsets, and ASics/FPgas. It can use up to 50% less space than traditional discrete power solutions and is the smallest solution in its class.

     The IR38163/5 and IR38363/5 are specifically designed to power Intel Vccio and Vcmp and servers that require SVID-enabled Intel chips. These devices do not need to be programmed because they are already pre-configured according to Intel requirements and specific numerical addresses. The IR38263/5 features a 3-bit parallel VID(PVID) for powering Intel chipsets PVNN and FPgas. It is ideal for telecommunications applications that require fixed frequency operation

     As well as network communication and storage applications that require large amounts of PMBus, precise Vout and ultra-low ripple.
The IPOL device product family uses the latest OptiMOSM5 technology and therefore offers significant efficiency benefits. In addition, the small 7mmx7mmPQFNCu-clip package allows the device to operate at high frequencies up to 30A, while not requiring a strong fan to dissipate heat. Pin-compatible options support with or without PMBus support. The product family uses Infineon's industry-leading PWM engine for ultra-low ripple and frequency jitter. They maximize noise reduction and increase bandwidth, while requiring less capacitance than other designs. Differential voltage sampling, a wide margining range and a reference voltage accuracy of 0.5% combine to achieve an output voltage accuracy of 1%.

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