Texas Instruments' low add-on jitter, low propagation delay clock buffer is designed to meet stringent performance requirements

Texas Instruments CDCDB400 is a four-output LP-HCSL, DB800ZL compliant clock buffer with low attached jitter and low propagation latency. The buffer is designed to meet the stringent performance requirements of PCIe Gen 1 to Gen 6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces in CC, SRNS, or SRIS architectures. The CDCDB400 allows buffering and copying of a single clock source, supporting up to four separate outputs in LP-HCSL format. The device also includes status and control registers accessible through the SMBus 2.0 compatible interface.

The clock buffer integrates external passive components to reduce overall system costs. CDCDB400 meets or exceeds the system parameters in the DB800ZL and DB2000Q specifications. The device comes in a 5 mm x 5 mm, 32 pin VQFN package.

Features

● Four LP-HCSL outputs with programmable integrated 85Ω (default) or 100Ω differential output terminals
● Four hardware outputs allow (OE#) control
● Additional phase jitter:

-   After PCIe Gen 6 filter: 20 fs, RMS (Max.)
-   After PCIe Gen 5 filter: 25 fs, RMS (Max.)
-   After DB2000Q filter: 38 fs, RMS (Max)

● Support for Universal clock (CC) and Independent reference (IR) architectures:

-   Compatible spread spectrum

● Output to output offset: < 50 ps
● Input-output delay: < 3 ns
● Fail-safe input
● Programmable output swing rate control
● Nine optional SMBus addresses
● 3.3V kernel and I/O supply voltage
● Hardware controlled Low Power mode (P #)
● Current consumption: 46 mA (Max.)
● Package: 5 mm x 5 mm 32 pin VQFN

Applications

● Microservers and tower servers
● Storage area network and host bus adapter card
● Network storage
● Hardware accelerator
● Rack server
● Communication exchange
● Modular computer
● CT and PET scanning machines
● Rugged PC laptop